1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an MOS transistor, in particular to a technology for realizing a higher speed and reduced power consumption by controlling a control potential (substrate potential or source potential) of the MOS transistor.
2. Description of the Related Art
A large-scale semiconductor integrated circuit in recent years enjoys a higher operation speed resulting from a higher integration thereof, while consuming a larger amount of electricity. When a power-supply voltage is reduced, power consumption can be accordingly reduced. However, the reduction of the power-supply voltage leads to a reduction of a current flow required for operating an MOS transistor, which interferes with the accelerated operation. A method for avoiding the inconvenience is to reduce an absolute value of a threshold voltage of the transistor in compliance with the reduction of the power-supply voltage, however the reduction of the absolute value of the threshold voltage results in a large volume of a leakage current flow of the transistor.
A possible solution to deal with such a problem is to connect a semiconductor substrate to a gate terminal when the transistor is in active mode and connect the same to a terminal of a substrate voltage smaller than a gate voltage when the transistor is on standby to thereby control the leakage current flow.
In the foregoing method, when a voltage for turning off the transistor, which is currently in the active mode, is applied to the gate, the same voltage is also applied to the semiconductor substrate. In such a situation, it is impossible to satisfactorily control the leakage current flow.